「Scalable Stochastic Number Duplicators for Accuracy-flexible Arithmetic Circuit Design」-情報処理学会

Scalable Stochastic Number Duplicators for Accuracy-flexible Arithmetic Circuit Design

［IPSJ Transactions on System and LSI Design Methodology Vol.13, pp.10-20］

［Abstract］

Stochastic computing is a computation method which can implement arithmetic operations by simple logic circuits. Stochastic numbers are used in this method, whose values are defined by their bit streams' appearance rates of 1's. As a nature of stochastic computing, changing the length of the input stochastic numbers will change the whole circuit's accuracy. However, in some implementations with re-convergence paths, the circuit itself will cause errors, i.e., the length of the input stochastic numbers does not change that circuit's accuracy. This paper proposes a stochastic number duplicator whose outputs differ every time and are all independent. This stochastic number duplicator has a scalable structure by changing the numbers of flip-flops for bit re-arrangement. From the experimental evaluations and discussions, we clarify that the proposed stochastic number duplicator enables accuracy-flexible circuits.

［Reasons for the award］

This paper provides a unified explanation of the fundamental causes behind the breakdown of flexible accuracy in stochastic computing from both theoretical and structural perspectives. It also proposes a novel stochastic number replicator as an efficient and effective solution to this issue, offering valuable guidelines for future hardware design in stochastic computing. Since it addresses a problem well suited for the scope of SLDM and presents a practical and impactful solution, the committee strongly recommends this paper as a candidate for the Best Paper Award.

Ryota Ishikawa

Ryota Ishikawa received the B. Eng., M. Eng., and Dr. Eng. degrees from Waseda University in 2018, 2019, and 2022, respectively, all in Computer Science. He joined IBM Japan, Ltd. in 2020, where he is presently engaged in enterprise data and AI system development. His research interests include stochastic computing, its related VLSI designs, image processing, machine learning and error corrections.

Masashi Tawada

Masashi Tawada received the B. Eng., M. Eng., and Dr. Eng. degrees in computer science from the Waseda University, Tokyo, Japan, in 2010, 2012, and 2015, respectively. He is currently an associate professor with the Green Computing Systems Research Organization, Waseda University. His research interests include cache design, embedded architecture, and non-volatile memory. He is a member of IEEE, IEICE and IPSJ.

Masao Yanagisawa

Masao Yanagisawa received the B. Eng., M. Eng., and Dr. Eng. degrees from Waseda University in 1981, 1983, and 1986, respectively, all in electrical engineering. He was with University of California, Berkeley from 1986 through 1987. In 1987, he joined Takushoku University. In 1991, he left Takushoku University and joined Waseda University, where he is presently a Professor in the Department of Electronic and Physical Systems. His research interests are combinatorics and graph theory, computational geometry, VLSI design and verification, and network analysis and design. He is a member of IEEE, ACM, IPSJ, and IEICE.

Nozomu Togawa

Nozomu Togawa received the B. Eng., M. Eng., and Dr. Eng. degrees from Waseda University in 1992, 1994, and 1997, respectively, all in electrical engineering. He is presently a Professor in the Department of Computer Science and Communications Engineering, Waseda University. His research interests are VLSI design, graph theory, and computational geometry. He is a member of IEEE, IPSJ, and IEICE.