The research focuses on adding custom instructions and corresponding HDL designs to RISC-V processors to accelerate depthwise separable convolution. Based on the cv32e40p open-source RISC-V processor, we have designed modules to perform Depthwise Convolution and Pointwise Convolution based on the characteristics of depthwise separable convolution. This improves the performance of the processor when running some specific lightweight neural network models, and the simulation is done using Verilator.