情報処理学会 第77回全国大会講演要旨

Network-on-Chip (NoC) is becoming mainstream in many-core designs. It is believed that the near future many-core architectures will have thousands of cores interconnected by NoC architectures. With such large scale architectures, the simulation time is a serious problem. Due to the ever increasing capacity of FPGAs, FPGA-based simulation is becoming a promising approach to the simulation speed problem. It is, however, still difficult to fit an NoC architecture with thousands of nodes to a single FPGA. Although multiple FPGAs can be used, this approach not only leads to a higher cost, but also makes the design become much more complex. Moreover, the off-chip communication becomes the performance bottleneck of the entire system. This paper proposes a novel time-division multiplexing approach which enables architects to fast and accurately emulate large scale NoC architectures using a single FPGA. For a given NoC architecture, instead of directly implementing it on an FPGA, we effectively utilize FPGA resources to emulate the behavior of the entire network using a small number of physical nodes.