情報処理学会 第75回全国大会講演要旨
6K-3
Flexible L1 cache optimization for a low power embedded system
Reducing a power consumption in a cache is an important problem in high performance and low power micro-processor systems, especially
in an embedded microprocessor.
In this paper, we propose a cache optimization method to meet a particular application. Our proposed method adjusts configuration parameters such as a cache size, a line size, an associativity and
so on, and then an L1 cache is reconfigured for an application program.
An effectiveness of this method will be verified by experiments using CACTI 6.5 and SPEC2006 benchmark on Simple-scalar 3.0d.
in an embedded microprocessor.
In this paper, we propose a cache optimization method to meet a particular application. Our proposed method adjusts configuration parameters such as a cache size, a line size, an associativity and
so on, and then an L1 cache is reconfigured for an application program.
An effectiveness of this method will be verified by experiments using CACTI 6.5 and SPEC2006 benchmark on Simple-scalar 3.0d.
