3K-7
Design of Synchronization Mechanism to Conquer the Clock Oscillator Variation for High Performance Stencil Computation Accelerator
○小林諒平,高前田ー山崎伸也,吉瀬謙二(東工大)
Stencil computation is one of the typical scientific computing kernels. It is applied diverse areas as Earthquake simulation, seismic imaging for the oil and gas exploration industry. We have proposed the effective stencil computation method and the architecture by employing multiple small FPGAs with 2Dmech topology. However, as we implemented stencil computation accelerator, we realized that the accelerator does not stable operate because clock oscillator variation occurs. This variation occurs because each FPGA node which composes the accelerator has unique clock domain.
In this paper, we evaluate clock oscillator variation quantitatively and describe design of synchronization mechanism to conquer the variation to operate the accelerator successfully.

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